RAM chips store each bit as a tiny electrical charge on a microscopic capacitor — charged means 1, empty means 0 — paired with one transistor per cell. Because that charge leaks away within milliseconds, the memory controller must constantly reread and rewrite every cell before it fades: a process called refresh. That upkeep is why it's called Dynamic RAM (DRAM).
The One-Transistor, One-Capacitor Cell
Nearly every RAM chip made since the 1970s uses the same basic building block: a single transistor and a single capacitor, referred to as a 1T1C cell. The capacitor is the actual storage element — a microscopic pair of plates that either holds a charge or doesn't. The transistor is a switch that connects that capacitor to a data line only when its row is selected. Multiply this pair by billions and arrange them in a grid, and you have a modern memory chip. The simplicity of the design is exactly what makes DRAM cheap: fewer parts per bit than any other common memory technology, which is why DRAM, not something faster, is what fills the memory slots on your motherboard.
Rows, Columns, and How a Cell Gets Addressed
Cells are arranged in a rectangular array, addressed the way a spreadsheet cell is: by row and column. To reach a specific bit, the controller first asserts a row address, which opens every transistor in that row and dumps the charge from an entire row of capacitors onto the array's sense amplifiers simultaneously. Only then does it select the specific column it actually wants. This two-step addressing is the origin of terms you'll see on spec sheets and in memory timings — RAS (Row Address Strobe) and CAS (Column Address Strobe) — and it's why opening a new row costs more time than reading a second column from a row that's already open. Memory controllers exploit this by keeping recently used rows open, which is one reason access patterns matter as much as raw clock speed for real-world performance.
Reading Is Destructive — and That's by Design
Here is the part that surprises people: reading a DRAM cell empties it. The read operation works by connecting the capacitor to a sense amplifier and measuring which way a tiny voltage tips — a measurement that drains the capacitor's charge in the process. If the chip did nothing else, the bit you just read would be gone. So immediately after sensing the value, the same sense amplifier writes it straight back into the capacitor before moving on. Every single read doubles as a rewrite. This isn't a flaw; it's baked into the cell's physics, and it quietly does half of the refresh workload for free.
Refresh: The Housekeeping That Never Stops
A DRAM capacitor holds its charge for only a few dozen milliseconds before leakage current drains it below a readable threshold. Left alone, every bit in the chip would silently revert toward zero. To prevent that, the memory controller walks through every row in the chip on a fixed schedule — typically once every 64 milliseconds for the whole array — reading each row and writing its value straight back in, exactly like the read-restore cycle above, but triggered proactively rather than by a program actually wanting that data. This refresh traffic competes with real read and write requests for access to the array, which is a real (if small) tax on performance and power; it's also precisely why removing power from a DRAM-based system erases its contents in a fraction of a second, unlike flash storage, which needs no power at all to hold a charge.
DRAM vs. SRAM: Why Your CPU Cache Uses Neither of These Tricks
The other common memory type, SRAM, stores each bit in a loop of four to six transistors that actively hold their state as long as power is applied — no capacitor, no leakage, no refresh. That makes SRAM faster and simpler to access, which is exactly why CPU cache is built from it. But six transistors per bit take far more silicon area than DRAM's one transistor and one capacitor, so SRAM is reserved for small, blazing-fast caches measured in megabytes, while DRAM — denser, cheaper, and refreshed in the background — fills the gigabytes of main memory that actually hold your operating system, open applications, and working files.
Why This Matters When You Buy RAM
Every generational jump in memory — DDR3 to DDR4 to DDR5 — is fundamentally about packing the same 1T1C cell more densely and running the read/refresh/rewrite cycle faster, not about reinventing how the cell stores a bit. A kit like Crucial's 32 GB DDR5-5600 kit and an older-generation kit such as Corsair's 32 GB DDR4-3200 kit both store bits with the exact mechanism described above; what changed between them is cell geometry, signaling speed, and internal bank parallelism, not the underlying physics. If you're deciding between generations or how much capacity to buy, our DDR4 vs. DDR5 guide and how much RAM do you need breakdown cover the practical side; this article is about what's actually happening inside the chip while your system runs.
Frequently Asked Questions
Why is it called "dynamic" RAM?
Because the stored charge is not stable on its own — it dynamically decays and must be actively refreshed dozens of times per second to survive. Static RAM (SRAM), by contrast, holds its state as long as power is applied, with no refresh needed.
Does refresh slow down my computer?
Marginally. Refresh traffic briefly blocks the row it's touching, but controllers schedule it to overlap with idle memory cycles whenever possible, so the real-world impact on everyday performance is small and already accounted for in a chip's rated speed.
What happens to RAM contents when you lose power?
They vanish almost immediately. Without power, refresh stops, capacitors drain, and every cell reverts to an unreadable state within a fraction of a second — which is exactly why RAM is described as volatile memory, unlike an SSD.
Is more RAM always faster?
Not directly — capacity and speed are separate specs. More capacity prevents slowdowns caused by running out of memory and swapping to disk; higher rated speed (MHz) and tighter timings affect how quickly the chip itself can be read and written.
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